Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences

  • Andreas Erik Hindborg, Pascal Schleuniger, Nicklas Bo Jensen, and Sven Karlsson. Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing DASIP, Madrid, Spain, 2014. doi:10.1109/DASIP.2014.7115604
    [BibTeX] [Abstract]

    Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications. The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.

    @InProceedings{2014-10-HINDBORG,
    author = {Andreas Erik Hindborg and Pascal Schleuniger and Nicklas Bo Jensen and Sven Karlsson},
    title = {{Hardware Realization of an FPGA Processor - Operating System Call Offload and Experiences}},
    booktitle = {{Proceedings of the Conference on Design and Architectures for Signal and Image Processing {DASIP}}},
    date = {2014-10-8/2014-10-10},
    address = {Madrid, Spain},
    doi = {10.1109/DASIP.2014.7115604},
    abstract = {Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications. The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.},
    year = {2014}
    }

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