Experiences with Compiler Support for Processors with Exposed Pipelines

  • Nicklas Bo Jensen, Pascal Schleuniger, Andreas Hindborg, Maxwell Walter, and Sven Karlsson. Experiences with Compiler Support for Processors with Exposed Pipelines. In Proceedings of the 22nd Reconfigurable Architectures Workshop (RAW 2015), pages 137-143, Hyderabad, India, 2015. doi:10.1109/IPDPSW.2015.9
    [BibTeX] [Abstract]

    Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30% fewer hardware resources. While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.

    @InProceedings{2015-05-JENSEN-2,
    author = {Nicklas Bo Jensen and Pascal Schleuniger and Andreas Hindborg and Maxwell Walter and Sven Karlsson},
    title = {{Experiences with Compiler Support for Processors with Exposed Pipelines}},
    booktitle = {{Proceedings of the 22nd Reconfigurable Architectures Workshop (RAW 2015)}},
    date = {2015-05-25},
    address = {Hyderabad, India},
    doi = {10.1109/IPDPSW.2015.9},
    pages = {137-143},
    abstract = {Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production compilers can successfully meet the strict constraints on instruction order and generate efficient object code. In this paper, we present our experiences developing a compiler backend using the GNU Compiler Collection, GCC. For a set of C benchmarks, we show that a Tinuso implementation with our GCC backend reaches a relative speedup of up to 1.73 over a similar Xilinx Micro Blaze configuration while using 30% fewer hardware resources. While our experiences are generally positive, we expose some limitations in GCC that need to be addressed to achieve the full performance potential of Tinuso.},
    year = {2015}
    }

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