Monthly Archives: April 2016

Programming Embedded Manycore: Refinement and Optimizing Compilation of a Parallel Action Language for Hierarchical State Machines

Programming Embedded Manycore: Refinement and Optimizing Compilation of a Parallel Action Language for Hierarchical State Machines

  • Ivan Llopard. Programming Embedded Manycore: Refinement and Optimizing Compilation of a Parallel Action Language for Hierarchical State Machines. PhD thesis, 2016.
    [BibTeX] [Abstract]

    Modeling languages propose convenient abstractions and transformations to handle the complexity of today’s embedded systems. Based on the formalism of Hierarchical State Machine, they enable the expression of hierarchical control parallelism. However, they face two importants challenges when it comes to model data-intensive applications: no unified approach that also accounts for data-parallel actions; and no effective code optimization and generation flows. In this thesis, we propose a modeling language extended with parallel action semantics and hierarchical indexed-state machines suitable for computationally intensive applications. Together with its formal semantics, we present an optimizing model compiler aiming for the generation of efficient data-parallel implementations.

    @PhdThesis{2016-04-LLOPARD,
    author = {Ivan Llopard},
    title = {{Programming Embedded Manycore: Refinement and Optimizing Compilation of a Parallel Action Language for Hierarchical State Machines}},
    institution = {Universit\'e Pierre \& Marie Curie, Paris},
    date = {2016-04-26},
    year = {2016},
    abstract = {Modeling languages propose convenient abstractions and transformations to handle the complexity of today's embedded systems. Based on the formalism of Hierarchical State Machine, they enable the expression of hierarchical control parallelism. However, they face two importants challenges when it comes to model data-intensive applications: no unified approach that also accounts for data-parallel actions; and no effective code optimization and generation flows. In this thesis, we propose a modeling language extended with parallel action semantics and hierarchical indexed-state machines suitable for computationally intensive applications. Together with its formal semantics, we present an optimizing model compiler aiming for the generation of efficient data-parallel implementations.}
    }

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Heterogeneous Computing with GPUs and FPGAs Through the OpenMP Task-Parallel Model

Heterogeneous Computing with GPUs and FPGAs Through the OpenMP Task-Parallel Model

  • Artur Podobas. Heterogeneous Computing with GPUs and FPGAs Through the OpenMP Task-Parallel Model. SIAM Conference on Parallel Processing for Scientific Computing, 2016.
    [BibTeX] [Abstract]

    The task-based programming model has become one the prominent models for parallelizing software on homogeneous shared-memory architectures. However, because Dennard’s scaling no longer holds, we have to leave homogeneity behind and move towards a more heterogeneous (possibly distributed) solution. In this talk, we will show how to extend the OpenMP task-model to support distributed computing through GPUs and how the model further can be used to drive hardware generation for FPGAs.

    @Misc{2016-04-PODOBAS,
    author = {Artur Podobas},
    title = {{Heterogeneous Computing with GPUs and FPGAs Through the OpenMP Task-Parallel Model}},
    howpublished = {SIAM Conference on Parallel Processing for Scientific Computing},
    date = {2016-04-12/2016-04-15},
    year = {2016},
    address = {Paris, France},
    organization = {Universit\'e Pierre \& Marie Curie},
    abstract = {The task-based programming model has become one the prominent models for parallelizing software on homogeneous shared-memory architectures. However, because Dennard's scaling no longer holds, we have to leave homogeneity behind and move towards a more heterogeneous (possibly distributed) solution. In this talk, we will show how to extend the OpenMP task-model to support distributed computing through GPUs and how the model further can be used to drive hardware generation for FPGAs.}
    }

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Single-Anchor Indoor Localization Using ESPAR Antenna

Single-Anchor Indoor Localization Using ESPAR Antenna

  • Mateusz Rzymowski, Przemys textbarl, and L. Single-Anchor Indoor Localization Using ESPAR Antenna. IEEE Antennas and Wireless Propagation Letters, 15:1183-1186, 2016. doi:10.1109/LAWP.2015.2498950
    [BibTeX]

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