Yearly Archives: 2014

The costs of fusion in smart camera networks

The costs of fusion in smart camera networks

  • Sandeep Katragadda, Juan C. SanMiguel, and Andrea Cavallaro. The costs of fusion in smart camera networks. In Proceedings of the International Conference on Distributed Smart Cameras, Venice, Italy, 2014. doi:10.1145/2659021.2659032
    [BibTeX] [Abstract]

    The choice of the most suitable fusion scheme for smart camera networks depends on the application as well as on the available computational and communication resources. In this paper we discuss and compare the resource requirements of five fusion schemes, namely centralised fusion, flooding, consensus, token passing and dynamic clustering. The Extended Information Filter is applied to each fusion scheme to perform target tracking. Token passing and dynamic clustering involve negotiation among viewing nodes (cameras observing the same target) to decide which node should perform the fusion process whereas flooding and consensus do not include this negotiation. Negotiation helps limiting the number of participating cameras and reduces the required resources for the fusion process itself but requires additional communication. Consensus has the highest communication and computation costs but it is the only scheme that can be applied when not all viewing nodes are connected directly and routing tables are not available.

    @InProceedings{2014-11-KATRAGADDA,
    title = {{The costs of fusion in smart camera networks}},
    author = {Sandeep Katragadda and Juan C. SanMiguel and Andrea Cavallaro},
    booktitle = {{Proceedings of the International Conference on Distributed Smart Cameras}},
    address= {Venice, Italy},
    date = {2014-11-04/2014-11-07},
    year = {2014},
    doi = {10.1145/2659021.2659032},
    abstract = {The choice of the most suitable fusion scheme for smart camera networks depends on the application as well as on the available computational and communication resources. In this paper we discuss and compare the resource requirements of five fusion schemes, namely centralised fusion, flooding, consensus, token passing and dynamic clustering. The Extended Information Filter is applied to each fusion scheme to perform target tracking. Token passing and dynamic clustering involve negotiation among viewing nodes (cameras observing the same target) to decide which node should perform the fusion process whereas flooding and consensus do not include this negotiation. Negotiation helps limiting the number of participating cameras and reduces the required resources for the fusion process itself but requires additional communication. Consensus has the highest communication and computation costs but it is the only scheme that can be applied when not all viewing nodes are connected directly and routing tables are not available.}
    }

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Cost-Aware Coalitions for Collaborative Tracking in Resource-Constrained Camera Networks

Cost-Aware Coalitions for Collaborative Tracking in Resource-Constrained Camera Networks

  • Juan C. SanMiguel and Andrea Cavallaro. Cost-Aware Coalitions for Collaborative Tracking in Resource-Constrained Camera Networks. IEEE Sensors Journal, 15(5):2657-2668, 2014. doi:10.1109/JSEN.2014.2367015
    [BibTeX] [Abstract]

    We propose an approach to create camera coalitions in resource-constrained camera networks and demonstrate it for collaborative target tracking. We cast coalition formation as a decentralized resource allocation process where the best cameras among those viewing a target are assigned to a coalition based on marginal utility theory. A manager is dynamically selected to negotiate with cameras whether they will join the coalition and to coordinate the tracking task. This negotiation is based not only on the utility brought by each camera to the coalition, but also on the associated cost (i.e. additional processing and communication). Experimental results and comparisons using simulations and real data show that the proposed approach outperforms related state-of-the-art methods by improving tracking accuracy in cost-free settings. Moreover, under resource limitations, the proposed approach controls the tradeoff between accuracy and cost, and achieves energy savings with only a minor reduction in accuracy.

    @Article{2014-11-SANMIGUEL,
    title={{Cost-Aware Coalitions for Collaborative Tracking in Resource-Constrained Camera Networks}},
    author={Juan C. SanMiguel and Andrea Cavallaro},
    journal={{IEEE Sensors Journal}},
    volume={15},
    number={5},
    pages={2657-2668},
    date={2014-11-04},
    year={2014},
    doi={10.1109/JSEN.2014.2367015},
    abstract={We propose an approach to create camera coalitions in resource-constrained camera networks and demonstrate it for collaborative target tracking. We cast coalition formation as a decentralized resource allocation process where the best cameras among those viewing a target are assigned to a coalition based on marginal utility theory. A manager is dynamically selected to negotiate with cameras whether they will join the coalition and to coordinate the tracking task. This negotiation is based not only on the utility brought by each camera to the coalition, but also on the associated cost (i.e. additional processing and communication). Experimental results and comparisons using simulations and real data show that the proposed approach outperforms related state-of-the-art methods by improving tracking accuracy in cost-free settings. Moreover, under resource limitations, the proposed approach controls the tradeoff between accuracy and cost, and achieves energy savings with only a minor reduction in accuracy.}
    }

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Cost-Effective Features for Reidentification in Camera Networks

Cost-Effective Features for Reidentification in Camera Networks

  • Syed Fahad Tahir and Andrea Cavallaro. Cost-Effective Features for Reidentification in Camera Networks. IEEE Transactions on Circuits and Systems for Video Technology, 24(8):1362-1374, 2014. doi:10.1109/TCSVT.2014.2305511
    [BibTeX] [Abstract]

    Networks of smart cameras share large amounts of data to accomplish tasks such as reidentification. We propose a feature-selection method that minimizes the data needed to represent the appearance of objects by learning the most appropriate feature set for the task at hand (person reidentification). The computational cost for feature extraction and the cost for storing the feature descriptor are considered jointly with feature performance to select cost-effective good features. This selection allows us to improve intercamera reidentification while reducing the bandwidth that is necessary to share data across the camera network. We also rank the selected features in the order of effectiveness for the task to enable a further reduction of the feature set by dropping the least effective features when application constraints require this adaptation. We compare the proposed approach with state-of-the-art methods on the iLIDS and VIPeR datasets and show that the proposed approach considerably reduces network traffic due to intercamera feature sharing while keeping the reidentification performance at an equivalent or better level compared with the state of the art.

    @Article{2014-02-TAHIR,
    title={{Cost-Effective Features for Reidentification in Camera Networks}},
    author={Syed Fahad Tahir and Andrea Cavallaro},
    journal={{IEEE Transactions on Circuits and Systems for Video Technology}},
    volume={24},
    number={8},
    pages={1362-1374},
    date={2014-02-11},
    year={2014},
    doi={10.1109/TCSVT.2014.2305511},
    abstract={Networks of smart cameras share large amounts of data to accomplish tasks such as reidentification. We propose a feature-selection method that minimizes the data needed to represent the appearance of objects by learning the most appropriate feature set for the task at hand (person reidentification). The computational cost for feature extraction and the cost for storing the feature descriptor are considered jointly with feature performance to select cost-effective good features. This selection allows us to improve intercamera reidentification while reducing the bandwidth that is necessary to share data across the camera network. We also rank the selected features in the order of effectiveness for the task to enable a further reduction of the feature set by dropping the least effective features when application constraints require this adaptation. We compare the proposed approach with state-of-the-art methods on the iLIDS and VIPeR datasets and show that the proposed approach considerably reduces network traffic due to intercamera feature sharing while keeping the reidentification performance at an equivalent or better level compared with the state of the art.}
    }

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Automatic Generation of Application Specific FPGA Multicore Accelerators

Automatic Generation of Application Specific FPGA Multicore Accelerators

  • Andreas Erik Hindborg, Pascal Schleuniger, Nicklas Bo Jensen, Maxwell Walter, Laust Brock-Nannestad, Lars Bonnichsen, Christian W. Probst, and Sven Karlsson. Automatic Generation of Application Specific FPGA Multicore Accelerators. In 48th Asilomar conference on Signals Systems and Computers, Pacific Grove, USA, 2014. doi:10.1109/ACSSC.2014.7094700
    [BibTeX] [Abstract]

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required. In this paper we propose a tool flow, which automatically generates highly optimized hardware multicore systems based on parameters. Profiling feedback is used to adjust these parameters to improve performance and lower the power consumption. For an image processing application we show that our tools are able to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator

    @InProceedings{2014-11-HINDBORG,
    author = {Andreas Erik Hindborg and Pascal Schleuniger and Nicklas Bo Jensen and Maxwell Walter and Laust Brock-Nannestad and Lars Bonnichsen and Christian W. Probst and Sven Karlsson},
    title = {{Automatic Generation of Application Specific FPGA Multicore Accelerators}},
    booktitle = {{48th Asilomar conference on Signals Systems and Computers}},
    date = {2014-11-02/2014-11-05},
    address = {Pacific Grove, USA},
    doi = {10.1109/ACSSC.2014.7094700},
    abstract = {High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required. In this paper we propose a tool flow, which automatically generates highly optimized hardware multicore systems based on parameters. Profiling feedback is used to adjust these parameters to improve performance and lower the power consumption. For an image processing application we show that our tools are able to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator},
    year = {2014}
    }

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Assessing Tracking Assessment Measures

Assessing Tracking Assessment Measures

  • Tahir Nawaz, Fabio Poiesi, and Andra Cavallaro. Assessing Tracking Assessment Measures. In Proceedings of the IEEE International Conference on Image Processing (ICIP), pages 441-445, Paris, France, 2014. doi:10.1109/ICIP.2014.7025088
    [BibTeX] [Abstract]

    We propose a methodology to quantitatively compare the relative performance of tracking evaluation measures. The proposed methodology is based on determining the probabilistic agreement between tracking result decisions made by measures and those made by humans. We use tracking results on publicly available datasets with different target types and varying challenges, and collect the judgments of 90 skilled, semi-skilled and unskilled human subjects using a web-based performance assessment test. The analysis of the agreements allows us to highlight the variation in performance of the different measures and the most appropriate ones for the various stages of tracking performance evaluation.

    @InProceedings{2014-10-NAWAZ,
    author = {Tahir Nawaz and Fabio Poiesi and Andra Cavallaro},
    title = {{Assessing Tracking Assessment Measures}},
    booktitle = {{Proceedings of the IEEE International Conference on Image Processing (ICIP)}},
    date = {2014-10-27/2014-10-30},
    address = {Paris, France},
    doi = {10.1109/ICIP.2014.7025088},
    pages = {441-445},
    abstract = {We propose a methodology to quantitatively compare the relative performance of tracking evaluation measures. The proposed methodology is based on determining the probabilistic agreement between tracking result decisions made by measures and those made by humans. We use tracking results on publicly available datasets with different target types and varying challenges, and collect the judgments of 90 skilled, semi-skilled and unskilled human subjects using a web-based performance assessment test. The analysis of the agreements allows us to highlight the variation in performance of the different measures and the most appropriate ones for the various stages of tracking performance evaluation.},
    year = {2014}
    }

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Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences

Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences

  • Andreas Erik Hindborg, Pascal Schleuniger, Nicklas Bo Jensen, and Sven Karlsson. Hardware Realization of an FPGA Processor – Operating System Call Offload and Experiences. In Proceedings of the Conference on Design and Architectures for Signal and Image Processing DASIP, Madrid, Spain, 2014. doi:10.1109/DASIP.2014.7115604
    [BibTeX] [Abstract]

    Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications. The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.

    @InProceedings{2014-10-HINDBORG,
    author = {Andreas Erik Hindborg and Pascal Schleuniger and Nicklas Bo Jensen and Sven Karlsson},
    title = {{Hardware Realization of an FPGA Processor - Operating System Call Offload and Experiences}},
    booktitle = {{Proceedings of the Conference on Design and Architectures for Signal and Image Processing {DASIP}}},
    date = {2014-10-8/2014-10-10},
    address = {Madrid, Spain},
    doi = {10.1109/DASIP.2014.7115604},
    abstract = {Field-programmable gate arrays, FPGAs, are attractive implementation platforms for low-volume signal and image processing applications. The structure of FPGAs allows for an efficient implementation of parallel algorithms. Sequential algorithms, on the other hand, often perform better on a microprocessor. It is therefore convenient for many applications to employ a synthesizable microprocessor to execute sequential tasks and custom hardware structures to accelerate parallel sections of an algorithm. In this paper, we discuss the hardware realization of Tinuso-I, a small synthesizable processor core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC CPU2006 benchmarks we show a speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27% to 35% fewer hardware resources.},
    year = {2014}
    }

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A Model-Driven Approach for Embedded System Prototyping and Design

A Model-Driven Approach for Embedded System Prototyping and Design

  • Nicolas Hili, Christian Fabre, Sophie Dupuy-Chessa, and Dominique Rieu. A Model-Driven Approach for Embedded System Prototyping and Design. In Proceedings of The IEEE International Symposium on Rapid System Prototyping (RSP), pages 23-29, New Delhi, India, 2014. doi:10.1109/RSP.2014.6966688
    [BibTeX] [Abstract]

    Embedded System (ES) development complexity is increasing. This increase has several cumulative sources: some are directly related to constraints on the ES themselves (dependability, compute intensive, resource constraints) while other sources are related to the industrial context of their development (fast prototyping, early validation, parallelization of developments). Although several Model-Driven Engineering (MDE) processes have been proposed for ES development, most of them are not completely formalized. This has several drawbacks that prevent their use in prototyping where iterations need to be short and focused. Incomplete formalized processes tend to be sidestepped in these situations where quick results are expected to be obtained with limited effort. In this paper we propose a MDE-based process for ES development. This process precisely defines the development tasks and their impact on the models throughout development. In particular we define iterations width and depth for the process that allow for a fined-grained and consistent planning of developments. The short and well defined iterations characterized by the process reduce the gap between rapid prototyping, ad-hoc methods and regular development processes.

    @InProceedings{2014-10-HILI,
    author = {Nicolas Hili and Christian Fabre and Sophie Dupuy-Chessa and Dominique Rieu},
    title = {{A Model-Driven Approach for Embedded System Prototyping and Design}},
    booktitle = {{Proceedings of The IEEE International Symposium on Rapid System Prototyping (RSP)}},
    date = {2014-10-16/2014-10-17},
    pages = {23-29},
    address = {New Delhi, India},
    doi = {10.1109/RSP.2014.6966688},
    abstract = {Embedded System (ES) development complexity is increasing. This increase has several cumulative sources: some are directly related to constraints on the ES themselves (dependability, compute intensive, resource constraints) while other sources are related to the industrial context of their development (fast prototyping, early validation, parallelization of developments). Although several Model-Driven Engineering (MDE) processes have been proposed for ES development, most of them are not completely formalized. This has several drawbacks that prevent their use in prototyping where iterations need to be short and focused. Incomplete formalized processes tend to be sidestepped in these situations where quick results are expected to be obtained with limited effort. In this paper we propose a MDE-based process for ES development. This process precisely defines the development tasks and their impact on the models throughout development. In particular we define iterations width and depth for the process that allow for a fined-grained and consistent planning of developments. The short and well defined iterations characterized by the process reduce the gap between rapid prototyping, ad-hoc methods and regular development processes.},
    year = {2014}
    }

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PENCIL: A platform-neutral intermediate language for the parallelizing compilation of DSLs

PENCIL: A platform-neutral intermediate language for the parallelizing compilation of DSLs

  • Ulysse Beaugnon, Riyadh Baghdadi, Javed Absar, Adam Betts, Albert Cohen, Alastair Donaldson, Tobias Grosser, Sven van Haastregt, Yabin Hu, Jeroen Ketema, Alexey Kravets, Anton Lokhmotov, and Sven Verdoolaege. PENCIL: A platform-neutral intermediate language for the parallelizing compilation of DSLs. Second Workshop on Domain-Specific Language Design and Implementation (DSLDI 2014), 2014. Held in conjunction with SPLASH/OOPSLA 2014
    [BibTeX]
    @Misc{2014-10-BEAUGNON,
    author = {Ulysse Beaugnon and Riyadh Baghdadi and Javed Absar
    and Adam Betts and Albert Cohen and Alastair Donaldson
    and Tobias Grosser and Sven van Haastregt and Yabin Hu
    and Jeroen Ketema and Alexey Kravets and
    Anton Lokhmotov and Sven Verdoolaege},
    title = {{PENCIL: A platform-neutral intermediate language for the parallelizing compilation of DSLs}},
    howpublished = {Second Workshop on Domain-Specific Language Design and Implementation (DSLDI 2014)},
    note = {Held in conjunction with SPLASH/OOPSLA 2014},
    date = {2014-10-19/2014-10-24},
    address = {Portland, OR, USA},
    year = {2014}
    }

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Unit Testing Framework for Operating System Kernels

Unit Testing Framework for Operating System Kernels

  • Maxwell Walter and Sven Karlsson. Unit Testing Framework for Operating System Kernels. Poster at the USENIX Symposium on Operating Systems Design and Implementation (OSDI), 2014.
    [BibTeX] [Download PDF]
    @Misc{2014-10-WALTER,
    author = {Maxwell Walter and Sven Karlsson},
    title = {{Unit Testing Framework for Operating System Kernels}},
    howpublished = {Poster at the USENIX Symposium on Operating Systems Design and Implementation (OSDI)},
    date = {2014-10-06/2014-10-08},
    year = {2014},
    address = {Broomfield, CO, USA},
    url = {http://orbit.dtu.dk/services/downloadRegister/104321268/poster_A0.pdf}
    }

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Detection of Irregularities on Automotive Semiproducts

Detection of Irregularities on Automotive Semiproducts

  • Erik Dovgan, Klemen Gantar, Valentin Koblar, and Bogdan Filipič. Detection of Irregularities on Automotive Semiproducts. In Proceedings of the 17th International Multiconference Information Society (IS 2014), pages 22-25, Ljubljana, Slovenia, 2014.
    [BibTeX] [Abstract] [Download PDF]

    The use of applications for automated inspection of semiproducts is increasing in various industries, including the automotive industry. This paper presents the development of an application for automated visual detection of irregularities on commutators that are parts of vehicle’s fuel pumps. Each type of irregularity is detected on a partition of the commutator image. The initial results show that such an automated inspection is able to reliably detect irregularities on commutators. In addition, the results confirm that the set of attributes used to build the classifiers for detecting individual types of irregularities and the priority of these classifiers significantly influence the classification accuracy.

    @InProceedings{2014-10-DOVGAN,
    author = {Erik Dovgan and Klemen Gantar and Valentin Koblar and Bogdan Filipi\v{c}},
    title = {{Detection of Irregularities on Automotive Semiproducts}},
    booktitle = {{Proceedings of the 17th International Multiconference Information Society (IS 2014)}},
    date = {2014-10-06/2014-10-10},
    pages = {22-25},
    address = {Ljubljana, Slovenia},
    url = {http://www.copcams.eu/wp-content/uploads/2014/10/Dovgan_etal_IS2014_Vol.A_22-25.pdf},
    abstract = {The use of applications for automated inspection of semiproducts is increasing in various industries, including the automotive industry. This paper presents the development of an application for automated visual detection of irregularities on commutators that are parts of vehicle’s fuel pumps. Each type of irregularity is detected on a partition of the commutator image. The initial results show that such an automated inspection is able to reliably detect irregularities on commutators. In addition, the results confirm that the set of attributes used to build the classifiers for detecting individual types of irregularities and the priority of these classifiers significantly influence the classification accuracy.},
    year = {2014}
    }

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